ABSTRACT
This chapter considers some of the fundamental design considerations that go into the design of a phase locked loop (PLL). Modeling plays a key role in the development of the PLL and it is imperative that the designer have an understanding of those models and the limitations inherent in any mathematical model. The architecture of the frequency synthesizer is often dependent upon the design of the receiver and exciter, and the PLL design engineer must take this fact and system requirements into account. The primary function of the PLL is to generate a band of transmit and receive injection frequencies that allow the receiver or transmitter to resolve the required channel spacing. The PLL makes a relatively unstable Voltage-controlled oscillator track the phase of the reference signal, which is derived from a stable crystal oscillator. Free running voltage controlled oscillators drift with variation in temperature and power supply noise, as well as noise on the control voltage line.
